1. Field of the Invention
The present invention is related to the field of circuits and methods for generating clock signals for a semiconductor memory, and more specifically to a multiphase clock generator and a method for generating an internal clock signal having a phase of an intermediate value relative to an external clock.
2. Description of the Related Art
Integrated circuits coordinate their operations through clock signals (also known as clocks).
Referring to FIG. 1, a circuit structure is shown for treating clock signals. The structure is described in more detail in U.S. Pat. No. 5,999,032.
Briefly, an external system clock XCLK is provided to generate an internal clock ICLK. The system clock XCLK is received by the input buffer IBUF. The input buffer IBUF has a delay time from the input of the system clock XCLK to the output of the input buffer IBUF that is designated d1.
The output of the input buffer IBUF is input to multiple internal buffers INTBUF (only one is shown), which output internal clock ICLK. The delay time for the internal buffer INTBUF is designated d2.
The internal clock ICLK is then transferred to the functional units within the integrated circuit chip. The internal clock ICLK will be the timing signal that is used to synchronize the transfer of the digital data from the internal circuits of an integrated circuit chip to the data input/output buffers, and to the data bus of the integrated circuit chip.
Referring now to FIG. 2, a timing diagram is shown for the circuit of FIG. 1. The external clock XCLK will be delayed or skewed by the delay d1 of the input buffer IBUF, plus the delay d2 internal buffer INTBUF. Since the timing of the functions of integrated circuits such as a SDRAM are determined by the internal clock ICLK, the access time T(acc) of the fetching or reading of the digital data from an SDRAM can be no smaller than the clock skew d1+d2.
As computer system clocks are approaching transfer rates of 100 MHz, it is desirable that the access time T(acc) of an SDRAM to be brought to +/xe2x88x920.1 ns of the period of the system clock XCLK. This means that any clock skew must be eliminated from the clock distribution system.
Phase Locked Loops (PLL) and Delay Locked Loops (DLL) are well known in the art for synchronizing two timing signals. In both cases the time to achieve synchronization or lock may be on the order of 50 cycles or more. With such long lock times in SDRAM applications, the internal clocking signals ICLK cannot be deactivated during the periods that the SDRAM is inactive. This will increase the power dissipation of the SDRAM to undesirable levels.
The Clock Synchronization Delay (CSD) is a class of synchronizing circuits that eliminate the clock skew d1+d2 within two clock cycles. Two types of CSDs known in the art are the latch type CSD and the nonlatched synchronous mirror delay (SMD).
Referring now to FIG. 3, a schematic diagram is shown for the general structure of a SMD circuit. As in FIG. 1, the system clock XCLK is received by the input buffer IBUF, and outputs a signal IBO, delayed by the delay d1. The output IBO of the input buffer IBUF is input to a delay monitor circuit DMC. The delay monitor circuit DMC will provide an output that is a delayed input signal IBO by a fixed amount. That fixed amount is usually designed to equal the sum of the delay d1 of the input buffer IBUF and the delay d2 of the internal buffer INTBUF.
The circuit of FIG. 3 includes three arrays, a forward delay array (FDA), an array of elements of a mirror control circuit (MCC), and a back delay array (BDA). These have corresponding elements.
The output of the delay monitor circuit DMC is input in forward delay array FDA. The forward delay array FDA is made from a number of delay elements. Each of those delay elements delays the input of the forward delay array FDA by an increment of time t(DF). The output of each delay element of the forward delay array FDA is input in each subsequent delay element, and is also one of the multiple outputs of the forward delay array FDA.
The multiple outputs of the forward delay array FDA are input in corresponding elements of a mirror control circuit MCC. The output IBO of the input buffer circuit IBUF is also provided to multiple inputs of the elements of mirror control circuit MCC. In each such element, the output IBO of the input buffer circuit IBUF is compared with each output of the forward delay array FDA. When one of the outputs of the forward delay array FDA is aligned with the n+1 pulse of the output IBO of the input buffer IBUF, the element of the mirror control circuit will transfer that one output to a corresponding element of the backward delay, array BDA. The mirror control circuit MCC will have multiple outputs to transfer any one of the inputs of the mirror control circuit MCC from the forward delay array FDA to the backward delay array BDA.
The backward delay array BDA is comprised of multiple delay elements. Each delays element has a delay time t(DF) equal to the delay time of the forward delay array FDA.
Referring now to FIG. 4, a timing diagram is shown for the circuit of FIG. 3. The delayed clock pulse will be delayed by a factor of:
t(FDA)=t(CK)xe2x88x92(d1+d2)
where:
t(CK) is the time of the period of the external clock, and
t(FDA) is the time of the period of the FDA, less the skew d1+d2.
The delayed clock pulse will be further delayed by the factor t(FDA) in the backward delay array BDA. Thus the nth pulse output of the backward delay array BDA will be delayed by a factor of:
2d1+d2+2[t(CK)xe2x88x92(d1+d2)]=xe2x88x92d2
This will make the nth pulse of the backward delay array BDA misaligned with the n+2 pulse of the system clock XCLK by a factor of the delay d2 of the internal buffer INTBUF.
The output of the backward delay array BDA will be the input of the internal buffer INTBUF. The nth internal clock ICLK will now be aligned with the system clock XCLK.
The mirror control circuit MCC can be of two types.
The first type can be a latch that will fix the delay segment of the forward delay element FDA selected to be transferred to the backward delay array BDA. Once the latch is set, it will only be reset during the inactivity time of the SDRAM. Upon reactivation of the SDRAM, the decision of the length of the delay necessary will be recreated.
The second type of mirror control circuit MCC can be the synchronous mirror delay (SMD). The mirror control circuit MCC will be a pass gate that is activated when the output of the forward delay circuit FDA is aligned with the n+1 pulse of the output IBO of the input buffer circuit IBUF. The synchronous mirror delay will choose on each cycle of the system clock XCLK, which of the delay elements is satisfactory to align with the output IBO of the input buffer circuit IBUF.
Referring now to FIG. 5, a detail is illustrated of a prior art embodiment that uses the second type of mirror control circuit (MCC). Circuit 500 has a FDA made of successive elements FD1, FD2, . . . , FDm, made from synchronous mirror delays (SMDs). Circuit 500 also has a BDA made of successive elements BD1, BD2, . . . , BDm, and a MCC array made of successive elements MCC1, MCC2, . . . , MCCm. A clock driver corresponds to internal buffer INTBUF.
The clock buffer receives the external clock signal Ext.CLK, and outputs an intermediate signal PCLK. Intermediate signal PCLK is delayed through a DMC (Delay Monitoring Circuit), and then input in the FDA. Then PCLK is compared with outputs of elements of the FDA at corresponding elements of the MCC.
In the case of FIG. 5, by-way of example, comparison is triggered at element MCC3, and the remainder of these arrays is unused. An in-phase locked FDA1 signal is output at MCC3. The FDA1 signal is delayed through a backward delay array (BDA) path selected by MCC3 to generate a BDA1 signal. The BDA1 signal passes through a clock driver to generate an internal clock INT.CLK. The backward delay array (BDA) is also associated with a dummy MCC array, having elements Dummy MCCn.
Referring now also to FIG. 6, an in-phase locked FDA1 signal is output at exactly one cycle after PCLK at MCC3. Such a SMD can make internal clock that is same phase in relation to external clock after only 2 cycles of the external clock.
When a delay of the clock buffer is designated td1, delay of the clock driver td2 and delay of the SMD delay unit T(du), a SMD is generally locked in two cycles. In other words, td1+tdmc+n*T(du)+n*T(du)+td2=2tclk, where tdmc1 is the delay time of DMC. Therefore, the delay of DMC may be advantageously set to equal td1+td2.
In general, if a locking operation is at the nth delay unit of a conventional SMD in FIG. 5, the locking operation can be indicated by the following:
(td1+td2)+n*T(du)=tclk @ conventional SMD lockingxe2x80x83xe2x80x83(Equation 1)
Int.CLK=Ext.CLK+td1+td1+td2+2(tclkxe2x88x92(td1+td2))+td2=Ext.CLK+2tclk
Even with the above structure, however, there is a problem in the conventional SMD. Even if it can generate an internal clock in-phased (0 degree) in relation to an external clock, it is impossible to lock it at phases of intermediate values, such as of 45, 90, 270, 325 degrees and the like.
One solution is taught in U.S. Pat. No. 5,999,032 which, however, is complicated. Another solution may be by using a DLL circuit. That, however, has disadvantages like requiring a complex design, and resulting in a long locking time.
Since input data may be aligned both with an edge of the external clock and a center portion of it, an open loop type of a clock delay line circuit is also needed for locking at phases having intermediate general values, such as 45, 90, 270 and 325 degrees.
The present invention overcomes these problems and limitations of the prior art. Generally, the present invention provides circuits and methods for generating an internal clock signal that has a phase of an intermediate value relative to an external clock.
A circuit made according to a general embodiment of the invention includes a clock buffer to generate an initial reference clock signal responsive to an external clock signal, a DMC to receive the initial reference clock signal, and an array of forward units to receive a signal from the DMC. The circuit also includes an array of back units that produces a back signal. The back signal is input in a clock driver to produce an internal clock signal. A delay element produces a delayed reference signal responsive to the initial reference clock signal. A plurality of MCCs receive an output of one of the forward units and the delayed reference clock signal. When one of the outputs of the forward units is synchronized with the delayed reference clock signal, one of the back units is thereby activated, which initiates generation of the back signal.
The invention offers the advantage that the generated internal clock signal has a controllable phase shift from the external clock signal. In addition, the advantages of the basic CSD structure are preserved.
The invention will become more readily apparent from the following Detailed Description, which proceeds with reference to the drawings, in which: